The present invention relates to synchronous semiconductor memory devices, and more particularly to an apparatus for adjusting a write latency of a synchronous semiconductor memory device.
Unlike a standard dynamic RAM (random access memory), a synchronous dynamic RAM can internally generate a column address (refer to a video RAM). In the standard dynamic RAM, since one column address must be supplied in order to read or write one data signal, there are needed n column addresses to read or write n data signals. Even if successive column addresses are used, this also applies (refer to a fast page mode and a static column mode). In the synchronous dynamic RAM, if only an initial column address is applied, the successive column addresses are internally generated, thereby reading or writing n data signals. Therefore, there is no need to externally supply all the column addresses. In the following specification, a counter referred to as a column address counter is used to determine the successive column addresses.
The number n of data signals which are capable of reading or writing after the initial column address is applied is referred to as a burst length or a wrap size. The burst length is not a fixed value but variable values varying with an address value received at when a mode reset signal (MRS) register is set, and these values are stored in an internal store register until the next MRS is set. Hence, the synchronous dynamic RAM stores data for controlling an internal circuit as well as data stored in a memory cell.
Unlike the standard dynamic RAM, the synchronous dynamic RAM uses the same clock in activating a column address strobe signal CAS and in receiving a column address. Latency represents the number of clock cycles that occurred of a system clock prior to data being generated or received since receipt of an initial column address, and this latency is counted by a clock unit. The latency in generating the data is referred to as a CAS latency or read latency, and the latency in receiving the data is referred to as a write latency. The CAS latency as well as the burst length is determined by the MRS. Generally, the write latency is fixed at any value.
In the synchronous dynamic RAM, since data signals corresponding to the burst length should be generated or received after the burst length is programmed to the MRS, it is necessary to detect when to internally stop data input/output. This is performed by comparing a counted clock with a value programmed to the MRS and stored in the register. A counter serving this purpose is referred to as a burst end counter.
In the synchronous memory device operated in synchronization with a frequency of the system clock externally applied, a write latency value depends on whether the data is received after how many clocks from the applied system clock. The memory device has been designed by fixing the write latency at one value. In order to meet a variety of user's demands for the write latency, to use complicated additional circuits may be undesirable on the part of the seller. Therefore, it is necessary to variably adjust the write latency to satisfy both the user and the seller.